//******************************************************************/
//脱机主控程序
//V0.1		2014/10/27 11:17:21	jzhang	
//******************************************************************/
`timescale	1ps/1ps
module VL908_G01(
		input	wire		sys_resetb,
                input	wire		sclkin,
                input   wire            key_in,
                
                output  wire            JP202_PIN3,
                output  wire            JP202_PIN4,
                output  wire            JP202_PIN5,
                input   wire            cpanel_key,
                
                output	wire		port_da,
                output	wire		port_db,
                inout	wire		sda,
                output	wire		scl,		
                

		//input	wire		flash_SO,      
		//output	wire		flash_SCK,     
		//output	wire		flash_SI,
		//output	wire		flash_CS_n,      

		output	wire		sa_clk,
		output	wire	[2:0]	sa_cnt,
		output	wire		sa_dqm_l,
		output	wire		sa_dqm_h,
		output	wire	[10:0]	sa_addr,
                output	wire	[1:0]	sa_bank,
		inout	tri	[31:0]	sa_data,
						
		output	wire		reset_phy,
		
		input	wire		gp0_rxc,
		input	wire		gp0_rxdv,
		input	wire	[3:0]	gp0_rxd,
		output	wire		gp0_txc,
		output	wire		gp0_txen,
		output	wire	[3:0]	gp0_txd,
		
		input	wire		gp1_rxc,
		input	wire		gp1_rxdv,
		input	wire	[3:0]	gp1_rxd,
		output	wire		gp1_txc,
		output	wire		gp1_txen,
		output	wire	[3:0]	gp1_txd,

		input	wire		mcu_mode,
		input	wire		mcu_spi_cs,
		input	wire		mcu_spi_clk,
		input	wire		mcu_spi_mosi,
		output	wire		mcu_spi_miso,
		input	wire		uart3_sync,
		
		input	wire		spi2_cs,
		input	wire		spi2_mosi,
		output	wire		spi2_miso,
		input	wire		spi2_clk,
					
		output	wire	[3:0]	fa_out,
		input	wire	[2:0]	fa_in,
		
		output	wire		sd_clk,
		inout	tri		sd_cmd_sdi,
		input	wire		sd_dat0_sdo,
		input	wire		sd_dat1,
		input	wire		sd_dat2,
		inout	tri		sd_dat3_cs,
				
		input	wire		sd_scd,
		input	wire		sd_swp,
		
		output	wire		mdc,
		inout	tri		mdio,
		
		output  wire    [7:0]	fa_d,
		output	wire    [7:0]	fa_le,
		output	wire    	fa_clk,
		output	wire    	fa_oe,
		
		input   wire            bd_clk,
		input   wire            bd_din,
		input   wire            bd_en,
		output  wire            bd_dout,
		
                output  wire            io_dir,
		inout	tri		led_g,
		output	wire		led_r,
		input   wire            in_nc_A
		);

//******************************************************************/
//			   参数定义
//******************************************************************/
parameter	Sim_Mode	=0;

//****************************************************************
//		内部信号
//****************************************************************
wire		oclk,tclk;
wire            resetb,lock_out;
wire		pll_reset;
wire		time_1ms,time_125ms,time_250ms;
wire		time_1ms_sync,time_16us_sync,time_15ms_sync,time_250ms_sync,time_1s_sync;

wire		gp0_rx_clk,gp1_rx_clk,sclk_in,sclk;

wire	[10:0]	obuf_raddr;
wire	[71:0]	obuf_rdata;
wire		out_clk;
wire		o_sync_flag,o_sclk,o_load,o_loeb;
wire	[4:0]	o_h_sel;
wire	[71:0]	o_data;
wire	[3:0]	adjust_bit;

wire		gp0_tx_en,gp1_tx_en;
wire	[7:0]	gp0_tx_data,gp1_tx_data;
wire		gp0_rx_dv,gp1_rx_dv;
wire	[7:0]	gp0_rx_data,gp1_rx_data;
wire		gp0_rec_flag,gp0_rec_error,gp1_rec_flag,gp1_rec_error,gp0_rec_error_t,gp1_rec_error_t;
wire		gp0_blank_flag,gp1_blank_flag,redu_flag,blank_flag;
wire		gp0_send_flag,gp0_pre_flag,gp1_send_flag,gp1_pre_flag;
wire	[7:0]	gp0_rec_data,gp1_rec_data,gp0_send_data,gp1_send_data;
wire		rec_flag,rec_error,send_flag,pre_flag;
wire	[7:0]	rec_data,send_data;
wire	[1:0]	rec_vendor;

wire		op_start_flag,fpga_rec_flag,fpga_rec_end,fpga_send_flag,fpga_send_end,send_buf_we;
wire	[7:0]	op_length;
wire	[31:0]	op_start_addr;
wire	[7:0]	rec_buf_raddr,rec_buf_rdata,send_buf_waddr,send_buf_wdata;

//wire		vs,hs;
wire	[7:0]	data;
wire    [10:0]  h_total_reg,l_total_reg,h_total,l_total;
wire		vs_a,hs_a;
wire	[7:0]	data_a;
wire	[10:0]	h_num_a,h_num_b;
wire	[15:0]	data_b;
wire	[5:0]	cycle_max;
wire            correct_pixel128,correct_enable;
wire	[10:0]	info_addr;
wire	[7:0]	info_data;
wire	[1:0]	unit_color_addr;
wire	[15:0]	unit_color_adj;
wire		unit_color_valid;
wire		adj_h_start,adj_rd_start2,adj_read_end;
wire	[8:0]	adj_h_num;
wire	[9:0]	adjust_addr;
wire	[47:0]	adjust_data;

wire		v_start;
wire		hs_b;

wire		init_mode,init_end,reboot_en_fpga,reboot_en,comm_en;
wire		flash_rec_end,flash_send_end,display_rec_end,display_send_end;
wire		flash_buf_we,display_buf_we;
wire	[7:0]	flash_buf_raddr,flash_buf_waddr,flash_buf_wdata;
wire	[7:0]	display_buf_raddr,display_buf_waddr,display_buf_wdata;
wire		read_start,read_end,read_d_ok,set_d_ok;
wire	[15:0]	set_addr;
wire	[23:0]	start_addr;
wire	[7:0]	read_data,set_data,state_addr;
wire	[7:0]	state_data,bd_state_data,state,state_2,fpga_state_data,dmx_state_data;

wire		black_mark;
wire    [7:0]   unit_pixel_w_max;

wire    [1:0]   pixel_mode;
wire	[4:0]	scan_num;
wire    [3:0]   bit_num;
wire	[7:0]	unit_num;
wire    [1:0]   color_count;
wire		obuf_sel,obuf_sync;
wire    [7:0]   unit_l_max;
wire            data_inv_en;
wire    [7:0]   unit_type;
wire    [4:0]	scan_h_max;
wire    [7:0]   signal_ctrl;
wire    [7:0]   shift_length_per_unit;

wire		flash_ms,input_active;
wire	[7:0]	no_vs_set;
reg		black_flag;

wire		shift_sync,display_sync,force_sync,more_adj_flag;
wire	[12:0]	shift_cycle_adj;

wire	[23:0]	sync_tout,o_tout;
wire		r_frame_sync;

//added by yluo@2010-12-1
wire		init_correct_d_ok;
wire	[18:0]	init_correct_addr;
wire	[7:0]   init_correct_data;
wire            load_picture_flag,load_adj_flag;
reg	[10:0]	key_reboot_count;
wire	[23:0]	tout,sd_tout;

wire            local_test_en,local_picture_en;
wire		press_detect;
wire            key_input;
wire            black;

wire            port_20_en,port_24_en,mode_port_free,empty_down,empty_right;
wire		flash_SO;      
wire		flash_SCK;     
wire		flash_SI;
wire		flash_CS_n;
wire            w_flag;
reg	[2:0]	reset_dcm_cnt;
reg		reset_dcm_flag;
reg		reset_dcm_150;
wire		clk_ok_n;
reg		clk_ok_n_t;
wire		tx_err_en;
wire            r_flag;
reg		init_end_flag=0;
wire            rec_error_sync;
wire    [8:0]   cascade_light;
wire    [7:0]   SR_set;
wire            o_hoeb;
wire            SR1,SR2; 

reg             set_state_ini,read_eeprom;
wire    [31:0]  read_eep_addr;
wire            read_eep_en;
wire            eep_d_ok;
wire    [7:0]   eep_data;    

wire	[7:0]	bd_wdata;
wire		bd_wen;
wire	[4:0]	bd_waddr;                  
wire    [4:0]   bd_raddr;
wire    [7:0]   bd_rdata;   

wire    [7:0]   table_unit_num,RVport_mode;
wire    [15:0]  unit_table_dout;
wire            cc_96_16;
wire            cc_128_16;
wire            cc_256_16;
wire            lc_256_8;    
wire    [8:0]   l_total_reg_b;
wire            h_b_end,h_b_start;
wire    [15:0]  g_tout;            
wire            RV_2,RV2_26pin;
wire    [79:0]  out;
wire	[7:0]	disp_tout,m_tout,correct_type;
wire	[31:0]	out_tout;
reg            testmode_ini_err;
wire            inner_led_g,press;

wire		t_500ns, t_us, t_ms, t_s;
wire	[1:0]	gp0_rx_type,gp1_rx_type;
wire		gp0_tx_clk,gp1_tx_clk,clk_25M;
wire		yt_vs_pre;
wire		clk_25M_neg;
wire		gp0_tx_clk_t,gp1_tx_clk_t;

wire	[31:0]	ep_start_blk;	//节目起始物理扇区
wire	[8:0]	ep_start_offset;//节目起始扇区内偏移
wire	[31:0]	ep_frame_max;	//节目总帧数
wire	[10:0]	ep_lnum;	//节目的一行总像素数
wire	[10:0]	ep_hnum;	//节目的总行数
wire	[12:0]	ep_lnum_byte;
wire		ep_out_start;
wire		offline_vs_en;
wire		sd_card_vaild;

//////////千兆输出模块////////////////
wire	[8:0]	rltime_raddr;
wire	[7:0]	rltime_rdata;
wire	[8:0]	subcom_raddr,audio_raddr,com_raddr;
wire	[7:0]	subcom_rdata,audio_rdata,com_rdata;
wire		subcom_en,audio_en,com_en;
wire		subcom_end,audio_end,com_end;
wire		subcom_flag,audio_flag;
wire		subcom_sel;
wire		rltime_sel;
wire		ddc_sel;
//wire		gp0_rx_clk,gp0_rx_dv,gp0_tx_clk,gp0_tx_en,gp1_rx_clk,gp1_rx_dv,gp1_tx_clk,gp1_tx_en;
//wire	[7:0]	gp0_rx_data,gp0_tx_data,gp1_rx_data,gp1_tx_data;
wire		disp_tx_en;
wire	[7:0]	disp_tx_data;

wire		config_send_en;
wire	[2:0]	config_type;
wire	[7:0]	config_raddr;
wire	[7:0]	config_rdata;
wire	[15:0]	config_mem_addr;
/////////mcu-fpga/////////////////////
wire		spi_rec_flag;
wire	[7:0]	spi_rec_data;
wire		spi_rec_error;
wire	[1:0]	spi_rec_vendor;

wire		spi_send_flag;
wire		spi_send_pre;
wire	[7:0]	spi_send_data;

wire		com2_op_start_flag,com2_rec_flag,com2_rec_end,com2_send_flag,com2_send_end,com2_send_buf_we;
wire	[7:0]	com2_op_length;
wire	[31:0]	com2_op_start_addr;
wire	[7:0]	com2_rec_buf_raddr,com2_rec_buf_rdata,com2_send_buf_waddr,com2_send_buf_wdata;

wire		mcu_rec_end,mcu_send_end,mcu_buf_we;
wire	[7:0]	mcu_buf_raddr,mcu_buf_waddr,mcu_buf_wdata;
wire		cmd_d_ok;
wire	[19:0]	cmd_addr;
wire	[7:0]	cmd_data;

wire	[7:0]	mcu_state_addr,mcu_state_data;
wire		mcu_state_active,mcu_offline_active;   

//////////////////////////////////////
//程序版本信息

parameter	SUB	=0;	   //分控
parameter	ASSIST	=1;	   //附属设备

parameter	ACTIVE	=1;
parameter	TEST	=2;	   
parameter	INIT	=3; 

//需要修改部分 start
parameter	MAIN_FUNCTION	=  8'h56;   //ASCII "V"  
parameter	SUB_FUNCTION	=  8'h4C;   //ASCII "L"  
parameter	MAIN_FSOLUTION	=  8'd9;    //"9"        
parameter	SUB_SOLUTION	=  8'd8;    //"08"       
parameter	APPLICATION_TYPE=  8'h47;   //ASCII "G"  
parameter	MAIN_VERSION	=  8'd1;    //"01"       
parameter	SUB_VERSION	=  8'd15;   //X" 07"  

parameter	MODE    =ACTIVE;//active, test, init

parameter	INIT_ADDR	=14'b0000_0000_1110_00;//0x00e0_0000~0x00e3_FFFF
parameter	TEST_ADDR	=14'b0000_0000_1110_01;//0x00e4_0000~0x00e7_FFFF
parameter	ACT_ADDR	=14'b0000_0000_1110_10;//0x00e8_0000~0x00eB_FFFF

defparam        com_ctrl.DEVICE_TYPE     	=ASSIST;//sub,assist
defparam        cascade_ctrl_a.DEVICE_TYPE   	=ASSIST;//sub,assist
defparam        cascade_ctrl_b.DEVICE_TYPE   	=ASSIST;//sub,assist
defparam        mcu_com_ctrl.DEVICE_TYPE     	=ASSIST;//sub,assist 

//需要修改部分 end

defparam	mcu_state.LOGIC_MODE		=MODE;
defparam	reboot_ctrl.LOGIC_MODE		=MODE;

defparam	com_ctrl.INITIAL_ADDR		=INIT_ADDR;
defparam 	com_ctrl.TEST_ADDR		=TEST_ADDR;
defparam  	com_ctrl.ACTIVE_ADDR		=ACT_ADDR;

defparam	mcu_com_ctrl.INITIAL_ADDR	=INIT_ADDR;
defparam 	mcu_com_ctrl.TEST_ADDR		=TEST_ADDR;
defparam  	mcu_com_ctrl.ACTIVE_ADDR	=ACT_ADDR;

defparam        state_ctrl_01.main_function   =	MAIN_FUNCTION;
defparam        state_ctrl_01.sub_function    =	SUB_FUNCTION;
defparam        state_ctrl_01.main_solution   =	MAIN_FSOLUTION;
defparam        state_ctrl_01.sub_solution    =	SUB_SOLUTION;
defparam        state_ctrl_01.application_type=	APPLICATION_TYPE;
defparam        state_ctrl_01.main_version    =	MAIN_VERSION;
defparam        state_ctrl_01.sub_version     =	SUB_VERSION;

defparam        mcu_state.main_function   =	MAIN_FUNCTION;             
defparam        mcu_state.sub_function    =	SUB_FUNCTION;                 
defparam        mcu_state.main_solution   =	MAIN_FSOLUTION;               
defparam        mcu_state.sub_solution    =	SUB_SOLUTION;                 
defparam        mcu_state.application_type=	APPLICATION_TYPE;             
defparam        mcu_state.main_version    =	MAIN_VERSION;                 
defparam        mcu_state.sub_version     =	SUB_VERSION;               

//对于1型卡 LOGIC 0 =FPGA2PORT LOGIC 1=PROT2FPGA
//对于2型卡 LOGIC 1 ==FPGA2PORT LOGIC 0=PROT2FPGA
//assign          io_dir=(chip_dmx_ack==1)?1:0;//'d0;
//test
assign		port_da=SR1;
assign		port_db=SR2;
assign		scl='d0;
assign		sda='d0;

//**************************************************************
//		时钟复位管理单元
//**************************************************************
wire	clk_150M;
wire	locked;
//in            sclkin,sys_resetb
//out           sclk,tclk,oclk,resetb      

//out           time_1ms_sync,time_1ms

//IBUFG sclk_in_m (.I(sclkin), .O(sclk_in));

//BUFG CLK0_BUFG_INST0 (.I(sclk_in), .O(sclk));

assign	oclk=(Sim_Mode==0)?clk_150M:sclk;
//assign	oclk=sclk;

sys_reset_ctrl sys_reset_ctrl(
        .sclkin(sclkin),
        .resetb(resetb),
        .reset_phy(reset_phy)
        );

detect_pll_unlock detect_pll_unlock(
	.sclk(sclk),
	.resetb(resetb),
	.key_input(key_input),
	.clk_ok_n(clk_ok_n),
	.tx_err_en(tx_err_en),
	.time_1ms_sync(time_1ms_sync),
	.init_end(init_end),
	.pll_reset(pll_reset)
);
//assign  pll_reset=~sys_resetb;

clk_gen	clk_gen_inst (
	//.areset ( 0),//pll_reset ),
	.inclk0 ( sclkin ),
	.c0 ( sclk ),//sclk
	.c1 ( clk_25M ),
	.c2 ( clk_25M_neg ),
	//.c3(sa_clk),
	.locked ( locked )
	);
	
clk_gen2        clk_gen_inst_2 (
                .areset ( pll_reset ),
                .inclk0 ( sclk ),
                .c0 ( clk_150M ),
                .c1(sa_clk),
                .locked (  )
                );

sys_timer       sys_timer(
                .resetb(resetb),
                .sclk(sclk),
                
                .time_500ns(t_500ns),
                .time_1us(t_us),
                .time_1ms(time_1ms),
                .time_125ms(time_125ms),
                .time_250ms(time_250ms),
                .time_1s(t_s),
                
                .time_1ms_sync(time_1ms_sync),
                .time_16us_sync(time_16us_sync),
                .time_15ms_sync(time_15ms_sync),
                .time_125ms_sync(time_125ms_sync),
                .time_250ms_sync(time_250ms_sync),
                .time_1s_sync(time_1s_sync)   
                );
                
assign	t_ms = time_1ms;
                
//**************************************************************/
//               面板接口
//**************************************************************/   
assign  key_input=press&cpanel_key;
assign  JP202_PIN3 = input_active;
assign  JP202_PIN4 = fpga_send_flag;
assign  JP202_PIN5 = send_flag;

//**************************************************************
//			整体控制
//**************************************************************
//in            init_end,fpga_rec_flag,op_start_flag,op_start_addr,
//out           init_mode,reboot_en,comm_en

//in            reboot_en

//in            rec_flag,rec_error;
//out           resetb,led_g,led_r,flash_ms,time_1ms  

//分控整体状态控制
s8_main_ctrl_01 main_ctrl(
		.resetb(resetb),
		.sclk(sclk),
		
		.init_end(init_end),
	        .input_active(1'b1),
		.key_active(1'b0),

		.fpga_rec_flag(fpga_rec_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),
		
		//模式控制
	        .init_mode(init_mode),
//	        .test_mode(),
		.reboot_en(reboot_en_fpga),
		.comm_en(comm_en),

		.tout(m_tout)
		);
		
//reboot
//icap_ctrl icap_ctrl(
		//.clk(sclk),
//		.rstn(resetb),
//		
//		.start_addr(24'h400000),
//		.addr_preload(1'b0),		//1: multi-boot address will preload during generating bit file
		//.start(reboot_en)
//		.busy()
   		//);

wire	[23:0]	reboot_addr;
reboot_ctrl reboot_ctrl(
		.sclk(sclk),
		.resetb(resetb),
		
	        .cmd_d_ok(cmd_d_ok),
	        .cmd_addr(cmd_addr),
	        .cmd_data(cmd_data),
	        
		.reboot_en_fpga(reboot_en_fpga),
		.reboot_addr(reboot_addr),
		.reboot_en(reboot_en)
	);
	
remote_sys remote_sys(
        .sclk(sclk),
        .reboot_en(reboot_en)
);

//always@(posedge sclk)
//        if(correct_type!=8'hA5)
//                testmode_ini_err<=1'b1;
//        else
//                testmode_ini_err<=1'b0;

//led状态指示
Led_Ctrl_SV2	Led_Ctrl_SV2(
		.resetb(resetb),
		.sclk(sclk),
		
		.time_ms(time_1ms),
                .time_250ms(time_250ms),

		.G_black(0),
		.G_flash(vs_gen_flag),//testmode_ini_err&rec_flag),

		.R_light(black_mark),
		.R_flash(rec_error_sync),

		.G_flash_1st(1'd1),
		.R_flash_1st(1'd0),
		
		.tx_err_en(tx_err_en),
		
		.nG_led(inner_led_g),
		.nR_led(led_r)
		);


ledG_press_IO ledG_press_IO(
                .sclk(sclk),
                .input_active(input_active),
                .detect_sync(time_15ms_sync),
                .sample_sync(time_1ms_sync),
                
                .inner_led_g(inner_led_g),
                .led_g(led_g),
                .key_in(key_in),
                .press(press)                
                );

//**************************************************************
//		   千兆级联模块
//**************************************************************    
//in    千兆A/B口输入信号
//out   千兆A/B口输出信号

//in    send_flag,pre_flag,send_data,flash_ms
//out   rec_flag,rec_data,rec_error,input_active  

clkmux	clkmux_inst_gp0 (
	.inclk ( gp0_tx_clk_t ),
	.outclk ( gp0_tx_clk )
	);

clkmux	clkmux_inst_gp1 (
	.inclk ( gp1_tx_clk_t ),
	.outclk ( gp1_tx_clk )
	);
	
RGMII_rec_io rec_io_a(
		.rst(~resetb),

		.rxc(gp0_rxc),
		.rxdv(gp0_rxdv),
		.rxd(gp0_rxd),		
			
		.rx_clk(gp0_rx_clk),
		.rx_dv(gp0_rx_dv),
		.rx_data(gp0_rx_data),

		.rx_er(),
		.rx_crs(),
		.rx_col()
		);
assign gp0_tx_clk_t=(gp0_rx_type==2)?clk_25M:sclk;
RGMII_trans_io trans_io_a(
		.rst(~resetb),

		.tx_clk(gp0_tx_clk),
		.tx_en(gp0_tx_en),
		.tx_data(gp0_tx_data),

		.tclk(gp0_tx_clk),//tclk),

		.txc(gp0_txc),
		.txen(gp0_txen),
		.txd(gp0_txd)		
		);

RGMII_rec_io rec_io_b(
		.rst(~resetb),

		.rxc(gp1_rxc),
		.rxdv(gp1_rxdv),
		.rxd(gp1_rxd),		
			
		.rx_clk(gp1_rx_clk),
		.rx_dv(gp1_rx_dv),
		.rx_data(gp1_rx_data),

		.rx_er(),
		.rx_crs(),
		.rx_col()
		);
assign gp1_tx_clk_t=(gp1_rx_type==2)?clk_25M:sclk;
//assign	gp1_rx_dv=0;	//测试用
//assign	gp1_rx_data=0;	//测试用

RGMII_trans_io trans_io_b(
		.rst(~resetb),

		.tx_clk(gp1_tx_clk),
		.tx_en(gp1_tx_en),
		.tx_data(gp1_tx_data),
//		.tx_en(0),	//测试用
//		.tx_data(0),	//测试用

		.tclk(gp1_tx_clk),//tclk),

		.txc(gp1_txc),
		.txen(gp1_txen),
		.txd(gp1_txd)
		);

v8_cascade_ctrl_01 cascade_ctrl_a(
		.resetb(resetb),
		.sclk(sclk),

		.rx_clk(gp0_rx_clk),
		.rx_dv(gp0_rx_dv),
		.rgmii_rx_data(gp0_rx_data),
		.rx_type(gp0_rx_type),
		
		.rec_flag(gp0_rec_flag),
		.rec_data(gp0_rec_data),
		.rec_error(gp0_rec_error),
		.blank_flag(gp0_blank_flag),

		.i_tx_en(gp1_send_flag),
		.i_tx_pre(gp1_pre_flag),
		.i_tx_data(gp1_send_data),
		
		.tx_clk(gp1_tx_clk),
		.tx_en(gp1_tx_en),
		.tx_data(gp1_tx_data),
		.tx_type(gp1_rx_type),
		.tx_err_en(tx_err_en),
		
		.disp_tx_en(disp_tx_en),
		.disp_tx_data(disp_tx_data),
		.input_active(input_active),
		
		.tout()
		);

v8_cascade_ctrl_01 cascade_ctrl_b(
		.resetb(resetb),
		.sclk(sclk),

		.rx_clk(gp1_rx_clk),
		.rx_dv(gp1_rx_dv),
		.rgmii_rx_data(gp1_rx_data),
		.rx_type(gp1_rx_type),
//		.rx_clk(0),
//		.rx_dv(0),
//		.rx_data(0),
		
		.rec_flag(gp1_rec_flag),
		.rec_data(gp1_rec_data),
		.rec_error(gp1_rec_error),
		.blank_flag(gp1_blank_flag),

		.i_tx_en(gp0_send_flag),
		.i_tx_pre(gp0_pre_flag),
		.i_tx_data(gp0_send_data),
		
		.tx_clk(gp0_tx_clk),
		.tx_en(gp0_tx_en),
		.tx_data(gp0_tx_data),
		.tx_type(gp0_rx_type),
                .tx_err_en(tx_err_en),

		.disp_tx_en(disp_tx_en),
		.disp_tx_data(disp_tx_data),
		.input_active(input_active),
		
		.tout()
		);

//端口选择
v8_port_select_01 port_select(
		.resetb(resetb),
		.sclk(sclk),
		
		.flash_ms(time_1ms),
                .time_125ms(time_125ms),

		.gp0_rec_flag(gp0_rec_flag),
		.gp0_rec_data(gp0_rec_data),
		.gp0_rec_error(gp0_rec_error),
		.gp0_blank_flag(gp0_blank_flag),
		
		.gp1_rec_flag(gp1_rec_flag),
		.gp1_rec_data(gp1_rec_data),
		.gp1_rec_error(gp1_rec_error),
		.gp1_blank_flag(gp1_blank_flag),
		
		.rec_flag(rec_flag),
		.rec_data(rec_data),
		.rec_error(rec_error),
		.rec_vendor(rec_vendor),
		.rec_error_sync(rec_error_sync),
		.yt_vs_pre(yt_vs_pre),
		
		.send_flag(send_flag),
		.pre_flag(pre_flag),
		.send_data(send_data),
		
		.blank_flag(blank_flag),
		.redu_flag(redu_flag),
		
		.gp0_send_flag(gp0_send_flag),
		.gp0_pre_flag(gp0_pre_flag),
		.gp0_send_data(gp0_send_data),
		
		.gp1_send_flag(gp1_send_flag),
		.gp1_pre_flag(gp1_pre_flag),
		.gp1_send_data(gp1_send_data),
		
		.input_active(input_active),
		
		.tout()
		);

//测试用
//assign	rec_flag=gp0_rec_flag;
//assign	rec_data=gp0_rec_data;
//assign	rec_error=gp0_rec_error;
		
//**************************************************************
//		通讯数据处理/上电初始化
//**************************************************************        
//in    rec_flag、rec_data、rec_error
//out   send_flag、pre_flag、send_data       
//out   set_d_ok、set_addr、set_data
//out   init_correct_d_ok、init_correct_addr、init_correct_data
//out   init_mode、init_end

//in/out   FLASH接口

//in    comm_en,init_mode
//out   init_end
                    
v8_com_ctrl_01 com_ctrl(
		.resetb(resetb),
		.sclk(sclk),
		.comm_en(comm_en),

		.rec_flag(rec_flag),
		.rec_error(rec_error),
		.rec_data(rec_data),
		.rec_vendor(rec_vendor),
		
		.send_flag(send_flag),
		.pre_flag(pre_flag),
		.send_data(send_data),
		
		.blank_flag(blank_flag),
		.redu_flag(redu_flag),
		.time_1ms_sync(time_1ms_sync),
		
		.fpga_rec_flag(fpga_rec_flag),
		.fpga_send_flag(fpga_send_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),
		.op_length(op_length),

		.fpga_rec_end(fpga_rec_end),	
		.rec_buf_raddr(rec_buf_raddr),
		.rec_buf_rdata(rec_buf_rdata),		

		.fpga_send_end(fpga_send_end),	
		.send_buf_we(send_buf_we),
		.send_buf_waddr(send_buf_waddr),
		.send_buf_wdata(send_buf_wdata),	
		
		.tout()
		);

v8_com_bus_01 com_bus(
		.resetb(resetb),
		.sclk(sclk),

		//和com_ctrl接口
		.fpga_rec_flag(fpga_rec_flag),
		.fpga_send_flag(fpga_send_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),

		.fpga_rec_end(fpga_rec_end),
		.rec_buf_raddr(rec_buf_raddr),

		.fpga_send_end(fpga_send_end),
		.send_buf_we(send_buf_we),
		.send_buf_waddr(send_buf_waddr),
		.send_buf_wdata(send_buf_wdata),	

		//和flash_ctrl接口
		.flash_rec_end(flash_rec_end),
		.flash_buf_raddr(flash_buf_raddr),

		.flash_send_end(flash_send_end),
		.flash_buf_we(flash_buf_we),
		.flash_buf_waddr(flash_buf_waddr),
		.flash_buf_wdata(flash_buf_wdata),	

		//和display_ctrl接口
		.display_rec_end(display_rec_end),
		.display_buf_raddr(display_buf_raddr),

		.display_send_end(display_send_end),
		.display_buf_we(display_buf_we),
		.display_buf_waddr(display_buf_waddr),
		.display_buf_wdata(display_buf_wdata),	

		.tout()
		);


//flash控制  
                
v8_flash_ctrl_02 flash_ctrl(
		.resetb(resetb),
		.sclk(sclk),

		//和通讯模块接口
		.fpga_rec_flag(fpga_rec_flag),
		.fpga_send_flag(fpga_send_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),
		.op_length(op_length),

		.rec_end(flash_rec_end),
		.rec_buf_raddr(flash_buf_raddr),
		.rec_buf_rdata(rec_buf_rdata),		

		.send_end(flash_send_end),
		.send_buf_we(flash_buf_we),
		.send_buf_waddr(flash_buf_waddr),
		.send_buf_wdata(flash_buf_wdata),	

		//和显示模块接口
		.read_start(read_start),
		.start_addr(start_addr),
		.read_end(read_end),
                .cc_128_16(cc_128_16), 
                		
		.read_d_ok(read_d_ok),
		.read_data(read_data),

		//和flash接口
	        .flash_SO(flash_SO),
		.flash_SCK(flash_SCK),
		.flash_SI(flash_SI),
		.flash_CS_n(flash_CS_n),

        	.tout()
		);

epcs_io epcs_io(
	.asdo_in(flash_SI),
	.asmi_access_granted(1'b1),
	.dclk_in(flash_SCK),
	.ncso_in(flash_CS_n),
	.noe_in(1'b0),
	.asmi_access_request(),
	.data0_out(flash_SO));
                    
//显示设置接口
display_bus_01 display_bus(
		.resetb(resetb),
		.sclk(sclk),
                
                .cc_96_16(1'b1),  
                .cc_128_16(1'b0), 
                .cc_256_16(1'b0),
                .lc_256_8(1'b0),                

		//和主控模块接口
		.init_mode(init_mode),
		.init_end(init_end),
		
		//和通讯模块接口
		.fpga_rec_flag(fpga_rec_flag),
		.fpga_send_flag(fpga_send_flag),
		.op_start_flag(op_start_flag),
		.op_start_addr(op_start_addr),
		.op_length(op_length),

		.rec_end(display_rec_end),
		.rec_buf_raddr(display_buf_raddr),
		.rec_buf_rdata(rec_buf_rdata),		

		.send_end(display_send_end),
		.send_buf_we(display_buf_we),
		.send_buf_waddr(display_buf_waddr),
		.send_buf_wdata(display_buf_wdata),	

		//和flash模块接口
		.read_start(read_start),
		.start_addr(start_addr),
		.read_end(read_end),
		
		.read_d_ok(read_d_ok),
		.read_data(read_data),

		//给显示逻辑的参数设置
	        .set_d_ok(set_d_ok),
	        .set_addr(set_addr),
	        .set_data(set_data),
		
		//逐点调整数据
		.init_correct_d_ok(init_correct_d_ok),
	        //.init_correct_addr(init_correct_addr),
	        .init_correct_data(init_correct_data),
	        .load_adj_flag(load_adj_flag),
	        .load_picture_flag(load_picture_flag),	        
		//和显示逻辑的状态读取
	        .state_addr(state_addr),
	        .state_data(state_data),
	        .bd_state_data(bd_state_data),
//	        .state_data(0),

		.badpoint_req(badpoint_req),		//读BUF请求
		.badpoint_ready(badpoint_ready),	//开始可以读buf的标志
		.badpoint_addr(badpoint_addr),		//读地址
		.badpoint_data(badpoint_data),		//读数据
		.badpoint_end(badpoint_end),		//读结束标志
		
 		.read_eep_en(read_eep_en),
                .read_eep_addr(read_eep_addr),
                .eep_d_ok(eep_d_ok),
                .eep_data(eep_data),
        	.tout(disp_tout)
		);
//状态寄存器
state_ctrl_02	state_ctrl_01(
		.resetb(resetb),
        	.sclk(sclk),

		//千兆PHY接口
		.rec_flag(rec_flag),
		.rec_error(rec_error),
		        
		//和通讯模块接口
		.set_addr(set_addr),
		.set_d_ok(set_d_ok),
		.set_data(set_data),
		.bad_p_max(bad_p_max),		
		//状态寄存器
		.state_addr(state_addr),
		.state_data(state_data),
		.fpga_rec_flag(fpga_rec_flag),
		
		//输出给led灯和输出控制模块
		.black_mark(black_mark)
		);
		

//**************************************************************
//		SDRAM接口
//**************************************************************
//assign	sa_clk 		= 0;
//assign	sa_cnt[2:0]	= 3'h0;
assign	sa_dqm_l	= 0;
assign	sa_dqm_h	= 0;
//assign	sa_addr[10:0]	= 11'h0;
//assign	sa_bank[1:0]	= 2'h0;

assign	bd_dout		= 0;//sd_tout[5];//0;


reg 		ccc, count_reset;
reg	[7:0]	sss, ccc_count;
wire		sd_cmd_oe, sd_dat_oe, sd_cmd_out;
wire	[3:0]	sd_dat_out;

//**************************************************************
//DEMO演示用，生成启动数据
//**************************************************************
wire		fpga_sd_flag;//vs_gen_flag;
demo_gen_flag demo_gen_flag(
			.sclk(sclk),
			.clk_25M(clk_25M),
			.resetb(resetb),
			
			.input_sync(uart3_sync),
			.t_ms(t_ms),
			.offline_vs_en(offline_vs_en),
			
			.sd_scd(sd_scd),
			
			.sd_card_vaild(sd_card_vaild),
			.fpga_sd_flag(fpga_sd_flag),
			.vs_gen_flag(vs_gen_flag)
			);
//**************************************************************
//		逻辑分析仪采样用
//**************************************************************
//测试信号选择
//assign	fa_le = (fa_in[1] == 1)?fa_d:{sd_cmd_oe, mcu_spi_miso, sd_dat3_cs, sd_dat2, sd_dat1, sd_dat0_sdo, sd_cmd_sdi, sd_clk};
assign	fa_le = (fpga_sd_flag==1)?fa_d:{sd_cmd_oe, mcu_spi_miso, sd_dat3_cs, sd_dat2, sd_dat1, sd_dat0_sdo, sd_cmd_sdi, sd_clk};
//assign	fa_le = (fa_in[1] == 1)?fa_d:{sd_cmd_oe, mcu_spi_miso, mcu_spi_mosi, crc_out_en, sd_cmd_en, cmd_data, sd_cmd_sdi, sd_clk};
//assign	fa_le = (fa_in[1] == 1)?fa_d:{mcu_spi_miso, sd_cmd_oe, sd_dat3_cs, sd_dat2, sd_dat1, sd_dat0_sdo, sd_cmd_sdi, sd_clk};
//assign	fa_le = (fa_in[1] == 1)?fa_d:{sd_cmd_oe, mcu_spi_miso, out_load, rec_load, rec_count_en, mcu_spi_cs, sd_cmd_sdi, sd_clk};

//待测时钟信号串移
always	@(posedge t_500ns)
	ccc <= fa_le[0];

always	@(posedge t_500ns)
	sss <= {sss[6:0], ccc};

//判断时钟信号是否有超时
always	@(posedge t_500ns)
	if (sss == 8'hff)
		count_reset <= 1;
	else
		count_reset <= 0;
		
//时钟计数（带超时复位）
always	@(negedge mcu_spi_clk or posedge count_reset)
	if (count_reset == 1)
		ccc_count <= 0;
	else
		ccc_count <= ccc_count + 1;



//**************************************************************
//		SPI->SD
//**************************************************************
wire		sd_clk_mcu,sd_clk_fpga;
wire		sd_cmd_oe_mcu,sd_cmd_oe_fpga;
wire		sd_cmd_out_mcu,sd_cmd_out_fpga;

mcu_sd_cnt mcu_sd_cnt(
		.resetb(resetb),
                .sclk(sclk),
                
		.mcu_mode(mcu_mode),
		.mcu_spi_cs(mcu_spi_cs),
		
		.mcu_spi_clk(mcu_spi_clk),
		.mcu_spi_mosi(mcu_spi_mosi),
		.mcu_spi_miso(mcu_spi_miso),
                
		.sd_clk(sd_clk_mcu),
		.sd_cmd_oe(sd_cmd_oe_mcu),
		.sd_cmd_out(sd_cmd_out_mcu),
		.sd_cmd_in(sd_cmd_sdi),
		.sd_dat_oe(sd_dat_oe),
		.sd_dat_out(sd_dat_out),
		.sd_dat_in({sd_dat3_cs, sd_dat2, sd_dat1, sd_dat0_sdo}),
		
		.tout()
		);

//cmd输出控制
assign	sd_cmd_sdi = (sd_cmd_oe == 1)?sd_cmd_out:1'bz;
	
//dat3输出控制
assign	sd_dat3_cs = (sd_dat_oe == 1)?mcu_spi_cs:1'bz;

//assign sd_cmd_oe=(fa_in[0]==1)?sd_cmd_oe_fpga:sd_cmd_oe_mcu;
//assign sd_cmd_out=(fa_in[0]==1)?sd_cmd_out_fpga:sd_cmd_out_mcu;
//assign sd_clk=(fa_in[0]==1)?sd_clk_fpga:sd_clk_mcu;

assign sd_cmd_oe=(fpga_sd_flag==1)?sd_cmd_oe_fpga:sd_cmd_oe_mcu;
assign sd_cmd_out=(fpga_sd_flag==1)?sd_cmd_out_fpga:sd_cmd_out_mcu;
assign sd_clk=(fpga_sd_flag==1)?sd_clk_fpga:sd_clk_mcu;

//assign sd_cmd_oe_fpga=1;
//assign sd_cmd_out_fpga=1;
assign sd_clk_fpga=clk_25M_neg;

wire		vsout;
wire		hsout;
wire		dsout;
wire	[10:0]	h_num;
wire	[7:0]	dout;
wire		stop_sel;


wire		read_stop;
//wire	[31:0]	ep_start_blk;	//节目起始物理扇区
//wire	[8:0]	ep_start_offset;//节目起始扇区内偏移
//wire	[31:0]	ep_frame_max;	//节目总帧数
//wire	[10:0]	ep_lnum;	//节目的一行总像素数
//wire	[10:0]	ep_hnum;	//节目的总行数

wire	[26:0]	vs_div;
wire		vs;

//参数配置
reg	[2:0]	vs_en_t;	
reg		vs_enable=0;
always @(posedge sclk)
	vs_en_t<={vs_en_t[1:0],~key_in};

always@(posedge sclk or negedge resetb)
	if(resetb==0)
		vs_enable<=0;
	else if(vs_en_t[2:1]==2'b10)
		vs_enable<=~vs_enable;
//	else
//		vs_enable<=0;

//**************************************************/
//			MCU-fpga	
//**************************************************/
vs_generator vs_generator(	
			.sclk(sclk),
			.resetb(resetb),
		
			.vs_div(vs_div),//2083333:60hz 4166666:30hz 5000000 25hz；6249999
			.vs_enable(vs_gen_flag),//(vs_enable),//(1),
			.vsout(vs)
		);
			
sdcard_interface sdcard_interface(
			.sclk(sclk),
			.resetb(resetb),
			.clk_25M(clk_25M),
			
			.t_ms(t_ms),
			.vsin(vs),//(vs),//(vs),//(~key_in),	//不一定是25M时钟，需要缓存
			.read_stop(0),
			.vs_enable(vs_gen_flag),
			
	       		.cmd_d_ok(cmd_d_ok),
	        	.cmd_addr(cmd_addr),
	        	.cmd_data(cmd_data),
//			.ep_start_blk(ep_start_blk),//32'h0000a11b),	//节目起始物理扇区
//			.ep_start_offset(ep_start_offset),//(0),//节目起始扇区内偏移
//			.ep_frame_max(ep_frame_max),//(470),	//节目总帧数
//			.ep_lnum(ep_lnum),//(264),	//节目的一行总像素数
			.ep_hnum(ep_hnum),//(128),	//节目的总行数
			.ep_lnum_byte(ep_lnum_byte),	//节目一行的总字节数
			.vs_div(vs_div),
			.sdhc_flag(),	//给读地址时，如果是老的SD卡，则是给字节数地址，如果是SDHC，则给block地址
			.read_busy(),
                        
			.sd_dat0_sdo(sd_dat0_sdo),
			.sd_dat1(sd_dat1),
			.sd_dat2(sd_dat2),
			.sd_dat3_cs(sd_dat3_cs),
			.sd_cmd_out(sd_cmd_out_fpga),
			.sd_cmd_oe(sd_cmd_oe_fpga),
			
			.sdcard_fpga(sdcard_fpga),
			.sd_clk(),
			.sd_card_vaild(sd_card_vaild),
			.sd_swp(),

			.vsout(vsout),
			.hsout(hsout),
			.dsout(dsout),
			.h_num(h_num),
			.dout(dout),
			.stop_sel(stop_sel),
			
			.tout(sd_tout)
				);
				
//**************************************************************
//		MCU与FPGA接口
//**************************************************************
mcu_interface_02 mcu_interface(
			.sclk(sclk),
			.resetb(resetb),
			
			.spi2_cs(spi2_cs),
			.spi2_mosi(spi2_mosi),
			.spi2_miso(spi2_miso),
			.spi2_clk(spi2_clk),
			
			.spi_rec_flag(spi_rec_flag),
			.spi_rec_data(spi_rec_data),
			.spi_rec_error(spi_rec_error),
			.spi_rec_vendor(spi_rec_vendor),
			
			.spi_send_flag(spi_send_flag),
			.spi_send_pre(spi_send_pre),
			.spi_send_data(spi_send_data),
			
			.tout()
				);

mcu_com_ctrl_01 mcu_com_ctrl(
		.resetb(resetb),
		.sclk(sclk),
		.comm_en(1),
                
		.rec_flag(spi_rec_flag),
		.rec_error(spi_rec_error),
		.rec_data(spi_rec_data),
		.rec_vendor(spi_rec_vendor),
		
		.send_flag(spi_send_flag),
		.pre_flag(spi_send_pre),
		.send_data(spi_send_data),
		
		.blank_flag(0),
		.redu_flag(0),
		.time_1ms_sync(time_1ms_sync),
		
		.fpga_rec_flag(com2_rec_flag),
		.fpga_send_flag(com2_send_flag),
		.op_start_flag(com2_op_start_flag),
		.op_start_addr(com2_op_start_addr),
		.op_length(com2_op_length),
                
		.fpga_rec_end(com2_rec_end),	
		.rec_buf_raddr(com2_rec_buf_raddr),
		.rec_buf_rdata(com2_rec_buf_rdata),		
                
		.fpga_send_end(com2_send_end),	
		.send_buf_we(com2_send_buf_we),
		.send_buf_waddr(com2_send_buf_waddr),
		.send_buf_wdata(com2_send_buf_wdata),	
                
		.tout()
		);

mcu_com_bus_01 mcu_com_bus(
		.resetb(resetb),
		.sclk(sclk),

		//和com_ctrl接口
		.fpga_rec_flag(com2_rec_flag),
		.fpga_send_flag(com2_send_flag),
		.op_start_flag(com2_op_start_flag),
		.op_start_addr(com2_op_start_addr),

		.fpga_rec_end(com2_rec_end),
		.rec_buf_raddr(com2_rec_buf_raddr),

		.fpga_send_end(com2_send_end),
		.send_buf_we(com2_send_buf_we),
		.send_buf_waddr(com2_send_buf_waddr),
		.send_buf_wdata(com2_send_buf_wdata),	

		//和mcu_ctrl接口
		.mcu_rec_end(mcu_rec_end),
		.mcu_buf_raddr(mcu_buf_raddr),
               
		.mcu_send_end(mcu_send_end),
		.mcu_buf_we(mcu_buf_we),
		.mcu_buf_waddr(mcu_buf_waddr),
		.mcu_buf_wdata(mcu_buf_wdata),	
		
		.tout()
		);
		
//显示设置接口
mcu_data_bus_01 mcu_data_bus(
		.resetb(resetb),
		.sclk(sclk),
                            
		//和主控模块接口
		.init_mode(0),
		
		//和通讯模块接口
		.fpga_rec_flag(com2_rec_flag),
		.fpga_send_flag(com2_send_flag),
		.op_start_flag(com2_op_start_flag),
		.op_start_addr(com2_op_start_addr),
		.op_length(com2_op_length),

		.rec_end(mcu_rec_end),
		.rec_buf_raddr(mcu_buf_raddr),
		.rec_buf_rdata(com2_rec_buf_rdata),		

		.send_end(mcu_send_end),
		.send_buf_we(mcu_buf_we),
		.send_buf_waddr(mcu_buf_waddr),
		.send_buf_wdata(mcu_buf_wdata),	


		//给MCU相关控制逻辑的接口设置
	        .cmd_d_ok(cmd_d_ok),
	        .cmd_addr(cmd_addr),
	        .cmd_data(cmd_data),
		       
		//读参数设置
		.mcu_offline_active(mcu_offline_active),
		.mcu_state_active(mcu_state_active),
	        .mcu_state_addr(mcu_state_addr),
	        .mcu_state_data(mcu_state_data),

        	.tout()
		);	
//状态寄存器
mcu_state_01	mcu_state(
		.resetb(resetb),
        	.sclk(sclk),
        	
		//写参数接口
	        .cmd_d_ok(cmd_d_ok),
	        .cmd_addr(cmd_addr),
	        .cmd_data(cmd_data),
	        
//	        .display_state(state),
	        //读参数接口
		.mcu_state_active(mcu_state_active),
		.mcu_offline_active(mcu_offline_active),
		.mcu_state_addr(mcu_state_addr),
		.mcu_state_data(mcu_state_data),  
		      
		//寄存器
		.sd_card_vaild(sd_card_vaild),
		//.sd_swp(sd_swp),
		.offline_vs_en(offline_vs_en)

		);
		
//**************************************************************
//		   SDRAM
//************************************************************** 
wire		w_sel,r_sel;
wire	[10:0]	w_h_num,r_h_num;
wire		hs,ds;
wire	[23:0]	sd_card_data;
wire		sdram_read,sdram_read_end;
wire	[9:0]	base_addr;
wire	[7:0]	r_length;
wire	[10:0]	r_addr;
wire	[31:0]	r_data;

wire		vs_convert,hs_convert,ds_convert;
wire	[31:0]	data_convert;
sdata_convert sdata_convert(
			.sclk(sclk),
			.resetb(resetb),
			
			.vsin(vsout),
			.hsin(hsout),
			.dsin(dsout),
			.din(dout),
			.h_num(h_num),
			.stop_sel(stop_sel),
			
			.vsout(vs_convert),
			.hsout(hs_convert),
			.dsout(ds_convert),
			.dout(data_convert),
			.w_sel(w_sel),
			.r_sel(r_sel),
			.w_h_num(w_h_num)
			);
			
sdram_vbuf sdram_vbuf(
			.resetb(resetb),
			.sclk(sclk),
		        
			.w_h_num({w_sel,w_h_num[9:0]}),	//本系统暂时支持最大2048行。
			.hin(hs_convert ),			//多于2048行的数据舍弃。
			.dsin(ds_convert),
			.din(data_convert),
                        
			.sdram_read(sdram_read),
			.sdram_read_end(sdram_read_end),
			.r_h_num({r_sel,r_h_num[9:0]}),
			.base_addr(base_addr),
			.rclk(sclk),
			.o_addr(r_addr),
			.o_data(r_data),
                        
			.sa_rclk(sclk),
			.sa_cnt(sa_cnt),
			.sa_dqm(sa_dqm),
			.sa_addr(sa_addr),
 			.sa_bank(sa_bank),
			.sa_data(sa_data)
      			  	);
 
//**************************************************************
//		   千兆输出模块
//**************************************************************     			  	
config_send config_send(
			.sclk(sclk),
			.resetb(resetb),
			
	       		.cmd_d_ok(cmd_d_ok),
	        	.cmd_addr(cmd_addr),
	        	.cmd_data(cmd_data),
			
			.config_send_en(config_send_en),
			.config_type(config_type),
			.config_mem_addr(config_mem_addr),
			.config_raddr(config_raddr),
			.config_rdata(config_rdata)	
			);        	
	       

rltime_com rltime_com(	
			.sclk(sclk),
			.resetb(resetb),

	       		.cmd_d_ok(0),//(cmd_d_ok),
	        	.cmd_addr(0),//(cmd_addr),
	        	.cmd_data(0),//(cmd_data),
	        	
			.rltime_raddr(rltime_raddr),
			.rltime_rdata(rltime_rdata)
			); 

sub_com	sub_com(	
			.sclk(sclk),
			.reset_n(resetb),
			.subcom_sel(),
			.mem_wren(),		
			.mem_addr(),
			.mem_wdata(),
			.rclk(sclk),
			.subcom_raddr(subcom_raddr),
			.subcom_rdata(subcom_rdata),
			.subcom_en(subcom_en), 
			.subcom_end(subcom_end) 
			); 
			
com_pkt_bus com_pkt_bus(	
			.reset_n(resetb),
			.rclk(sclk),
			
			.subcom_raddr(subcom_raddr),
			.subcom_rdata(subcom_rdata),
			.subcom_en(subcom_en),
			.subcom_end(subcom_end),
			
			.audio_raddr(audio_raddr),
			.audio_rdata(audio_rdata),
			.audio_en(audio_en),
			.audio_end(audio_end),

			.subcom_flag(subcom_flag),
			.audio_flag(audio_flag),
			.com_raddr(com_raddr),
			.com_rdata(com_rdata),
			.com_en(com_en),
			.com_end(com_end)
		);
		
gmii_dis_trans 	gmii_dis_trans(
			.rst_n(resetb),
			.rclk(sclk),
			
			.vsin(vs_convert), //display_en & vs_vir,		//暂不开放display_en功能
			.v_sync(v_sync),
			
			.row_max(ep_hnum),//(128),
			.col_max(ep_lnum_byte),//(792),	

			.sdram_read(sdram_read),     		//读操作起始标志
			.sdram_read_end(sdram_read_end),     	//读操作结束标志
			.r_h_num(r_h_num),        		//读取的SDRAM行地址
			.row_count(row_count),
			.base_addr(base_addr),			//读取的SDRAM基本列地址
			.r_length(r_length),
			.r_addr(r_addr),	        	//SDRAM输出BUF地址
			.r_data(r_data),         		//SDRAM输出BUF数据

			.rltime_raddr(rltime_raddr),
			.rltime_rdata(rltime_rdata),

			.config_send_en(config_send_en),
			.config_type(config_type),
			.config_mem_addr(config_mem_addr),
			.config_raddr(config_raddr),
			.config_rdata(config_rdata),	
			
                	.p0_subcom_en(0),
                	.p1_subcom_en(0),			
			.subcom_flag(0),
			.audio_flag(0),			
			.com_raddr(),
			.com_rdata(0),
			.com_en(0), 
			.com_end(), 
			
			.p0_tx_en(disp_tx_en),			//发送使能
			.p0_tx_data(disp_tx_data),		//发送数据
			.p1_tx_en(),			//发送使能
			.p1_tx_data(),		//发送数据
			
			.tout(test_gen)
			);

//******************测试信号输出*************************
//assign	fa_clk = (fa_in[0]==1)?sclk:t_500ns ;//(fa_in[0]==1)?sclk:t_500ns ;//t_500ns;//
assign	fa_clk = (fpga_sd_flag==1)?sclk:t_500ns ;
assign	fa_oe = ccc_count[7]& sd_tout[0] & sd_tout[1] & sd_tout[2] & sd_tout[3] & sd_tout[4] & sd_tout[5] & sd_tout[6] & sd_tout[7];
assign	fa_out = {sd_dat2,sd_cmd_sdi, mcu_spi_clk, mcu_spi_cs};
//assign	fa_in = {mcu_spi_cs, sd_dat0_sdo, sd_dat2};

///////////////////////////////////////
rx_clk_check	rx_clk_check_p0(
	.sclk(sclk),
	.rx_clk(gp0_rx_clk),	
	.clk_type(gp0_rx_type)
	);

rx_clk_check	rx_clk_check_p1(
	.sclk(sclk),
	.rx_clk(gp1_rx_clk),	
	.clk_type(gp1_rx_type)
	);
	             
endmodule

